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| VHDL/Verilog Editor under Linux | ||
| Author 398338 Views 14 Posted at 2008/8/26 02:44 [View In Forum] | ||
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What is the best VHDL/Verilog Editor to be used under Linux.. jawcpkt guide me also to its web and tutorials if any .jawcpkt Thanks jawcpkt Mohamed Salem |
| Reply No. | Replier | Total Replies 28 [View All Replies] [New Reply] | Replied at |
| 1 | edu | VHDL/Verilog Editor under Linux Most editors have support for vhdl/verilog. Under unix some of the more popular editors are vim, nedit, and emacs/xemacs. I've used vim/gvim for many years under solaris and linux and it has served me well. I even made it my main windows editor a couple of years back. You can find vim at vim.org. Editors are a pretty personal thing. You really just have to try a couple and see which one you like best. Radix |
2008/8/26 02:44 |
| 2 | chdd | VHDL/Verilog Editor under Linux yeah, vim/gvim is great & free, it's can work on linux/solaris/windows. |
2008/8/26 02:44 |
| 3 | htc2498 | VHDL/Verilog Editor under Linux I always use Vi ,because it is strong enough to edit verilog/VHDL . |
2008/8/26 02:44 |
| 4 | netlgc | VHDL/Verilog Editor under Linux Hi, I use only Emacs for writing of VHDL codes. For some guys it's a little bit strange editor but it's very good, fast strong and it serves you also predefined VHDL structures. Example: you write in the process part only if |
2008/8/26 02:44 |
| 5 | spacebac | VHDL/Verilog Editor under Linux I think Vi is suitable for editingVerilog. |
2008/8/26 02:44 |
| 6 | gao51755775 | VHDL/Verilog Editor under Linux you can try emacs with verilog-mode.el |
2008/8/26 02:44 |
| 7 | mxg330 | VHDL/Verilog Editor under Linux gvim, nedit and emacs are some of the VHDL/Verilog editors available for linux. I prefer gvim. |
2008/8/26 02:44 |
| 8 | wy830115 | VHDL/Verilog Editor under Linux why not use jedit!? |
2008/8/26 02:44 |
| 9 | zunwang | VHDL/Verilog Editor under Linux emacs with verilog mode is very powerful. The 'AUTO' modes are very useful; saves typing a lot and help prevent stupid typo bugs. For example, missing variables in sensitivity list can be prevented using 'AUTO'. We are designing a huge (big die) network processor at 2 GHz and all of us are using emacs with veriolg mode. Try it.
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| 10 | ct731 | VHDL/Verilog Editor under Linux using nedit is good and simple. HDL Designer of Mentor is good, too. |
2008/8/26 02:44 |
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