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| Verilog problem Array sizing | ||
| Author rickli Views 2 Posted at 2008/8/28 06:51 [View In Forum] | ||
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Hi,maqofdrcy maqofdrcy maqofdrcy maqofdrcy maqofdrcy maqofdrcy I want to set arraysize based on the max value to be represented. Is this possible in verilog?maqofdrcy maqofdrcy maqofdrcy i.e.maqofdrcy maqofdrcy maqofdrcy maqofdrcy maqofdrcy maqofdrcy parameter CLK_DIV = 27210;maqofdrcy maqofdrcy maqofdrcy maqofdrcy maqofdrcy maqofdrcy reg [14..0]CLK_DIV_REG; //<<-- how do I set this array size automatically for when I change the parameter. |
| Reply No. | Replier | Total Replies 4 [View All Replies] [New Reply] | Replied at |
| 1 | fujun2013 | parameter CLK_DIV = 27210; reg [CLK_DIV-1 : O] CLK_DIV_REG; or parameter CLK_DIV =27210; reg [31:0] CLK_DIV_REG [CLK_DIV-1 :0]; |
2008/8/28 06:51 |
| 2 | zunwang | Thanks. But I worked out how to do it in the end. Your example will give 27209 bits to represent a number that is one big number. Here is the way that works. parameter CLK_DIVISION_FACTOR = 131; localparam DIV_BITS = clog2(ADC_CLK_DIVISION_FACTOR); //define the clogb2 function //this function returns the celing of the log2 of an input value // ie log2(200) returns 8 (8 bits to represent) function integer clog2; input [31:0] value; begin value = value - 1; for (clog2 = 0; value > 0; clog2 = clog2 1) value = value >> 1; end endfunction the function must be in the module. I am using a `include to include it in the module. |
2008/8/28 06:51 |
| 3 | ybyygu | that's impossible to realize your intent by such writing. early ASSEMBLER language can support such writing. best regards |
2008/8/28 06:51 |
| 4 | mxg330 | i don't think it's a good idea. if u need do this .i think you should use built-in RAM in FPGA. | 2008/8/28 06:51 |
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