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| To declare a user defined primitive in Verilog | ||
| Author anuo2008 Views 2 Posted at 2008/8/28 06:38 [View In Forum] | ||
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Hi All,uhiazec uhiazec uhiazec uhiazec uhiazec uhiazec Below is the example code I am trying to Synthesize in Xilinx ISE 8.1:uhiazec uhiazec uhiazec uhiazec uhiazec uhiazec ///////////////Example code to declare a UDP and use it in a module////////////////////////uhiazec uhiazec uhiazec |
| Reply No. | Replier | Total Replies 3 [View All Replies] [New Reply] | Replied at |
| 1 | zunwang | Hi I want to ask do you have passed compilation on any other tool. thanks |
2008/8/28 06:38 |
| 2 | stgod | No, as of now the only tool I have access to is Xilinx ISE 8.1. What other tools are you looking at??? I think it should work even on Xilinx ISE cuz I have pulled up the example code from Xilinx web resources... This information can be found here: http://toolbox.xilinx.com/docsan/xilinx7/help/iseguide/mergedProjects/hdledit/html/verilog_primitive.htm. Thanks Jayanth |
2008/8/28 06:38 |
| 3 | knoxville | According to the XST guide, UDP is not supported for synthesis. That means it can be used in simulation only. See http://toolbox.xilinx.com/docsan/xilinx8/books/docs/xst/xst.pdf |
2008/8/28 06:38 |
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