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| Xilinx ML 401 | ||
| Author ct731 Views 2 Posted at 2008/8/28 06:28 [View In Forum] | ||
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Hello , omptgaf omptgaf omptgaf I have a problem , I try to write vhdl code and i need a delay , it means that i have to omptgaf omptgaf omptgaf set the signal to '0' , wait some time and then change the state to '1' . And I dont know how to make that delay. I tried to use wait statement but it doesn't work(The compiler says that synthesis doesn't support this kind of statement). I need a delay about a few microseconds. Does anybody know how to resolve it ?? |
| Reply No. | Replier | Total Replies 2 [View All Replies] [New Reply] | Replied at |
| 1 | yvling | make a counter and load it with any number u want (according to ur clock frequency and the delay u want) and then make it decrement and when it reaches zero, then it means times is up and u can proceed with anything after that |
2008/8/28 06:28 |
| 2 | ai8957382 | That's correct. Use a high-speed clock and a counter. Synthesis tools generally don't support delay statements because an FPGA usually doesn't include any predictable delay elements. |
2008/8/28 06:28 |
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