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| DDS Help | ||
| Author bubulu Views 13 Posted at 2008/8/28 06:14 [View In Forum] | ||
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anyone please help . iwpjxv iwpjxv iwpjxv tell me the step to come out with DDS iwpjxv iwpjxv iwpjxv 120 MHZ iwpjxv iwpjxv iwpjxv 8 bit iwpjxv iwpjxv iwpjxv iwpjxv iwpjxv iwpjxv please help |
| Reply No. | Replier | Total Replies 29 [View All Replies] [New Reply] | Replied at |
| 1 | htc2498 | Are you using a Xilinx device? Which one? Try the "DDS Compiler" or "Direct Digital Synthesizer" cores included with Xilinx ISE CORE Generator. Or build your own DDS. Feed a frequency constant into an ordinary arithmetic accumulator. Connect the accumulator output to the address inputs of a sinewave lookup table ROM. The ROM output is your digital sinewave. |
2008/8/28 06:14 |
| 2 | naoge | Xilinx okies i got my 8bit but i don know what happen it only show me the wave half way . from 0000 to 0101001 the rest nothing .... i don know why . any one help~~ please |
2008/8/28 06:14 |
| 3 | fujun2013 | What software are you using to display the wave? If it defaults to unsigned value display, then you should configure it to display signed values (both positive and negative). In ModelSim, right-click the signal's name in the wave window, select Properties, and then explore the various options. | 2008/8/28 06:14 |
| 4 | ct731 | err i got a wave and but it only showing iit half way | 2008/8/28 06:14 |
| 5 | gao51755775 | err i got my 8 bit signal half way . it stop and all the way become red line . there's my test banch ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS COMPONENT dds PORT( clk : IN STD_LOGIC; sclr: STD_LOGIC; SINE: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; SIGNAL clk: std_logic:='1'; SIGNAL SINE: std_logic_vector(7 downto 0); SIGNAL sclr : std_logic; BEGIN uut: dds PORT MAP( sclr=>sclr, clk=>clk, SINE=>SINE ); sclr <= '1','0' after 0.1 ns; tb : PROCESS BEGIN clk <= not clk after 1 ns; wait for 1 ns; END PROCESS tb; END; anyone help ~ please:cry: |
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| 6 | anuo2008 | What is the name of the software that's showing you the incorrect waveform? Can you show us a screen image of the malfunction you see? Have you configured your waveform viewer to show signed (positive and negative) values? In your VHDL testbench, where is your "DDS" component? If it's a core, which one did you use, and what parameters did you specify to create it? Your testbench simulates fine in ModelSim 6.3c. I generated an 8-bit DDS core using Xilinx coregen and "DDS Compiler 2.0". The clock is 500 MHz, the sinewave is 120 MHz. Here's a screen image. The vertical scale on the "sine" signal is from -128 to 127: |
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| 7 | naoge | MOdelSim XE III/Starter 6.1e - Custom Xilinx i using Direct Digital Synthesizer 5.0 this is what i get sad |
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| 8 | booksir | this is what i got | 2008/8/28 06:14 |
| 9 | yvling | err how to check whether the vertical scale on the "sine" signal is from -128 to 127 . and is there a way you can shift the whole "sine" singal to upper the Zero like moving the whole sine above zero |
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| 10 | knoxville | Wow, I didn't expect to see that! Your 'sine' signal is displayed as simple binary, so it has no vertical scale. Earlier, when you said it was displaying only "half way", I thought you meant in the vertical direction, not in the horizontal direction. My comments about signed and unsigned therefore don't apply. The Xilinx DDS core shouldn't run at all during the first 100ns, because the FPGA's global reset signal is active. Your signals are somehow active before that time, and then become undefined after a few clock cycles. Also, your signals appear to change on the *negative* edge of the clock instead of the positive edge. Very strange! Your screen snapshot shows only the first 35ns. Does anything interesting happen after 100ns? To display the "sine" signal as an analog waveform (like my snapshot), right-click the signal name, click Properties, change the radix to decimal, change the format to analog, change the offset to 128, change the scale to 0.5, and change the height to 128. I've never seen a malfunction like your display. I don't know what's wrong. Maybe it's an installation/configuration problem between ISE and ModelSim. Be sure you have installed all the available ISE and IP service packs. Which version of Xilinx ISE are you using? Your screen snapshot looks like a pre-route simulation. Is that correct, or is it a post-route simulation? If it's a post-route simulation, then I don't think any Xilinx device can run the DDS core at 500 MHz, so maybe that's what's wrong. Does ModelSim give you any timing warning messages? Maybe you could zip up all your project files and upload them somewhere, so someone could try to figure out what's going wrong. |
2008/8/28 06:14 |
Total Replies 29 Thread Per Page 10
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