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| XST ERROR 1534 | ||
| Author fusarium Views 12 Posted at 2008/8/28 06:12 [View In Forum] | ||
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Hello,jiwvuoq jiwvuoq jiwvuoq jiwvuoq jiwvuoq jiwvuoq My VHDL code for Horizontal counter seems to compile without errors, however during the synthesizing process in ISE, it gives me the following error:jiwvuoq jiwvuoq jiwvuoq jiwvuoq jiwvuoq jiwvuoq ERROR:Xst:1534 - Sequential logic for node <value> appears to be controlled by multiple clocks. |
| Reply No. | Replier | Total Replies 4 [View All Replies] [New Reply] | Replied at |
| 1 | ybyygu | You are asking ISE to create both a register output (first part of process) and a latch output (second part of process) for the same signal. The first part is a register pattern because of clock event. The second part is a latch pattern because it is not part of the register pattern, and also because the output (looks like a destination) signal is not specified for every case. Specifying the state of value |
2008/8/28 06:12 |
| 2 | stgod | well, totally remaked this code. now i dont get exactly this warning. but i get the following ones: WARNING:Xst:1989 - Unit <VGActrl>: instances <R[0].RED_OUT>, <R[1].RED_OUT> of unit <AND_3> are equivalent, second instance is removed |
2008/8/28 06:12 |
| 3 | ybyygu | You need to look at the ISE software manuals. |
2008/8/28 06:12 |
| 4 | wy830115 | well, i changed the code, now i think it is ok: | 2008/8/28 06:12 |
Total Replies 4 Thread Per Page 10
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