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| insufficient LE units | ||
| Author bubulu Views 10 Posted at 2008/8/28 06:09 [View In Forum] | ||
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I am currently doing ASIC design for my project, when i tried to prototype the device in FPGA for testing, the device cannot fit in due to LE usage too high.ncxwur ncxwur ncxwur ncxwur ncxwur ncxwur I tried to put my design into APEX NIOS2 board, which uses APEX 20K200EFC484-2X FPGA. My design consisted own sequential access RAM for the device function purpose. ncxwur ncxwur ncxwur ncxwur ncxwur ncxwur Any recommandation to solve this prob??? |
| Reply No. | Replier | Total Replies 3 [View All Replies] [New Reply] | Replied at |
| 1 | knoxville | I don't know much about your design. But generally any FPGA has a limited space for logic. Fore sure you cannot have a very big design in a little FPGA. But you can do somethings: 1- try to estimate your logic count and compare it with FPGA capacity. If they are close together you can change architecture or even cut some part to fit it in fpga. otherwise try larger FPGA. |
2008/8/28 06:09 |
| 2 | z315 | thx to both of u, I had just continued & expanded with more details I able to explain (I am kind of fresh in this area, sorry :p) this question at: http://www.edaboard.com/viewtopic.php?p=1021374#1021374 |
2008/8/28 06:09 |
| 3 | ken7976 | there is a lot of examples | 2010/6/8 12:24 |
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