Homepage   Forum     WEB     BBS  
Thread List  
Forum Guide Map  
Thread Content             
 Homepage  >> RFEDA FORUM  >> ASIC
   
AGC loop design problem
Author nnxd   Views 2   Posted at 2008/8/28 05:04  [View In Forum]
Hikpavp
kpavp
Does anyone know how to design an AGC loop for a 70MHz bandwidth signal?kpavp
kpavp
The output of the AGC will be supplied to a fast 160MHZ A/D.kpavp
kpavp
What are the main design topology, which parts are preferred to used,kpavp
kpavp
Does anyone have a schematic of such a design?kpavp
kpavp
kpavp
kpavp
I will be very grateful,kpavp
kpavp
Thanks
      

Reply No. Replier Total Replies 0   [View All Replies]  [New Reply] Replied at
No replies currently or prohibitted to show
 Total Replies 0  Thread Per Page 10
Page 1/0  |<  <<     >>  >| 
Power by DiY-Page 5.3.0 RLC