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| layout | ||
| Author knoxville Views 12 Posted at 2008/8/28 05:00 [View In Forum] | ||
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I'm getting a bit confused these days about the word "layout"vbawksimdy vbawksimdy is it the making of the mask layers for the IC ?vbawksimdy vbawksimdy or is it the process of floorplanning and place & route ?vbawksimdy vbawksimdy vbawksimdy vbawksimdy or are they at the end allll extensions to each other???vbawksimdy vbawksimdy vbawksimdy vbawksimdy in an ASIC, when exactly do I do the mask layout for each transistor?vbawksimdy vbawksimdy when it's a small design, or it's always done this way....???vbawksimdy vbawksimdy vbawksimdy vbawksimdy should i see the P&R plan then do according to it the mask layout or what?vbawksimdy vbawksimdy vbawksimdy vbawksimdy I'm confused about terminology and hierarchy of steps vbawksimdy vbawksimdy vbawksimdy vbawksimdy vbawksimdy vbawksimdy thanks,vbawksimdy vbawksimdy Salma |
| Reply No. | Replier | Total Replies 29 [View All Replies] [New Reply] | Replied at |
| 1 | btcdtc | hi, I am beginer of layout. As I know, the basic layout is draw each transistor by youself.But now,we have some EDA tools such SE/Astro,this tools can auto P&R. | 2008/8/28 05:00 |
| 2 | z4120356 | 2008/8/28 05:00 | |
| 3 | scuzt | ahaaaa so i do the "each single transistor" layout when it's just the first time to do this design (full custom), cause there isn't a previous designed cell to be placed nor routed....but if the cells are already there (standard cells), then obviously i just need to connect them and no need for the making of their masks since they're already ready in the fab of course what are the output file types of each stage please? thanks, Salma |
2008/8/28 05:00 |
| 4 | nnxd | vary a lot....layout is always gds,sometimes tool specific format also as Magma gives lava(they are very inspired by the geographical terms I guess) as output .. but it is not easy to give you view list..can you please streamline it to some specific design steps... |
2008/8/28 05:00 |
| 5 | 398338 | hello salma at every stage the layout file is given out as .gds only . along with other files like .lef or .sdf or .spef ./.many files are generated at this stage for various verfication like timing. Suresh |
2008/8/28 05:01 |
| 6 | z4120356 | i was just confused about the fact that we say layout about p&r and also about the mask layout but now i know the difference between them, for instance if i have a full custom ASIC, i'll be doing the mask layout for my cells (cause they'll be somehow unique) and then i'll generate a symbol (i guess) which is then used in a library for the p&r tool (if it isn't custom then the p&r tool will use the fab standard cells)... and if i have a standard cell ASIC, then i won't need to do the mask layout for my cell cause they'll be already designed by the fab and now also i know that it's usually a GDS extension for layout (representing the geomertical shapes and the labels of the layout)....but for p&r ? what's the output ? is it also GDS or any other tool specific extension or something else??? am i missing something guys? or confusing stuff? Salma |
2008/8/28 05:01 |
| 7 | bubulu | 2008/8/28 05:01 | |
| 8 | knoxville | hello salma please check the following link . may be u can get a good picture of P&R steps. http://vcag.ecen.okstate.edu/projects/scells/flow/encounter_gui/index.html BEST OF LUCK Suresh |
2008/8/28 05:01 |
| 9 | ybyygu | Hi Suresh, can you please share some more links??? Thanks... |
2008/8/28 05:01 |
| 10 | stgod | hello deh There are lot of simple tutorials thse are mostly university slides .. i will try to send u more .. but from ur side i suggest u to look into the uni slides which offer vlsi courses .. Best of luck suresh Added after 2 minutes: |
2008/8/28 05:01 |
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