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| linear regulator - high frequency (200kHz~10MHz) smoothing | ||
| Author btcdtc Views 33 Posted at 2008/8/26 23:45 [View In Forum] | ||
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I am in trouble again.fnajn fnajn fnajn fnajn I have a SMPS regulator, which is then followed by a linear regulator (quasi LDO). The problem is the high frequency spikes (smps regulator has a nominal operating frequency of 200kHz) feed directly through my linear regulator. I am trying to design a linear regulator that could have about 60dB smoothing from 200kHz to 10MHz, but apparently I have no idea what am I doing. Only thing I could think of and that has brought me (some) success is to use a cascode output stage. And this gives mixed results. fnajn fnajn fnajn fnajn Does anyone have any ideas? What could help my linear regulator?fnajn fnajn fnajn fnajn fnajn fnajn Ran some simulations in multisim and then in Spice3 and apparently those two won't agree. Which makes it even better. |
| Reply No. | Replier | Total Replies 6 [View All Replies] [New Reply] | Replied at |
| 1 | wy830115 | The noise is going to apear on hte output unless a post Lc filter & Y decoupling caps are not introduced before LDO (after SMPS) the main reason is the radiated noise from SMPS gets picked up on the wires / tracks & gets converterd to conducted noise. |
2008/8/26 23:45 |
| 2 | bubulu | I tried simply filtering the smps output with a LC (100uH and 2200uF) as suggested, but this caused the linear regulator to oscillate. Now this oscillation was so big, that the linear regulator falled out of regulation and started drawing more current into the load, which in turn triggered the smps current limit and the smps started oscillating too. I abandoned the idea of filtering with the LC filter, instead I will try a small RF choke that hopefully will eat the high frequency sikes, but then the fundamental 200kHz ripple will be still there. I tried with a RC (100n poly and R from mohm to 5.6 ohm) on the smps output too. No effect at all. Attachment is an previous HW iteration. Shows the basic principle. R19 is where Vref from an DAC comes in. IC7 is for current limiting. This schematic does not have the cascode output transistor and asociated circuitry. EDIT: Ignore C35, 100nF. That was just stupid. EDIT1: what does hte mean? |
2008/8/26 23:45 |
| 3 | z4120356 | The strong compensation of your error amplifier is apparently the reason, why the circuit has poor 200 kHz ripple rejection. Reviewing the data of commercial IC, you'll find 30 to 40 dB typically. That isn't much, but should be sufficient in most cases, assuming that the input voltage wouldn't have extensive ripple. A pre- or post filter of course affects the regulator stability (it has also an impact at the switching regulator loop), but it's an approbate means. Filter parameters and regulator compensation have to be tuned in a suitable way. |
2008/8/26 23:45 |
| 4 | booksir | Read these they may give you some ideas. Minimizing switching-regulator residue in linear-regulator outputs |
2008/8/26 23:45 |
| 5 | knoxville | I would suggest passive filter in front of linear regulator. Higher freq are easier to address with passive, while lower end you could further suppress by linear regulator. If you make design that powers your error amplifier with output voltage, you could get better performance. In linear design floating psu for error amplifier might be easier to control. |
2008/8/26 23:45 |
| 6 | bubulu | put few cerimic caps (1ua and 0.1u) at the output of your smps. Lower the overall ESR will give you smaller ripple. | 2008/8/26 23:45 |
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