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| Title | Author | Views/Replies | Posted at |
 error correction circuit for 1.5bit/stage pipelined ADCCan someone please provide some good reference on how to design error correction circuit for 1.5b/stage pipelined ADC? If detailed circuit topology/schematic can be provided, that'll be greatly apprec... |
knoxville | 4/6 | 2008/8/27 15:34 |
| Look at Figure 2.53(b) of Razavi's Design of Analog CMOS IC I know there must be VX>VG /VTHP/, but I really can't imagine how the voltage of the drain terminal of both the two transistors changes, I can't get a formula or anything else to describe it, can some... |
rickli | 4/5 | 2008/8/27 15:11 |
| Virtuoso-XL Does anyone know that Virtuoso-XL Chip Assembly router can help on mix-signal design? such as automatic shielding clock signal, take care differential pair. |
hualeyan | 12/1 | 2008/8/27 15:45 |
| Calibre LVS output error Hello every body ,,, I looking for some info about calibre interactive. I am using cadence virtouso to make some layouts for 0.35um tech and for DRC , LVS and PEX I'am using mentor calibre interact... |
spacebac | 4/3 | 2008/8/27 14:35 |
| Cadence Cell Design Tutorial Error I following the Cadence Cell Design Tutorial for layout, cadence version is ic5141. I work well for the tutorial until in chapter4( "/doc/celltut/chap4.html) , that is running LVS with the extracted ... |
z4120356 | 3/3 | 2008/8/27 14:53 |
| about passive current mirror i just find a problem in Rzavi's book 《design of anglog cmos integrated circuits》 in chap 5,there is mentioned "passive current mirror & active current mirror" but i dont konw what'... |
htc2498 | 4/3 | 2008/8/27 15:27 |
| Load Capacitor for Inverter (TSMC 0.25 um) Hi All, If I want to use TSMC 0.25um CMOS to design logic gate, like inverter, nand ... How much of the load capacitor I should choose when I do the simulation? If I use 50 fF, is it reasonable? ... |
scuzt | 5/3 | 2008/8/27 15:42 |
| Who can tell me some startup technologies for bandgap There are few such materials about startup circuits for bandgap in IEEE. Where can I find relative materials? Thank you! |
netlgc | 3/6 | 2008/8/27 15:30 |
| MEMORY Circuits Experts Hi All, Memory experts please help me explain the following: 1. Memory Architecture 2. Addressing schemes 3. Sensing Schemes 4. I/O schemes Please help me explain on this topic because i h... |
anuo2008 | 5/6 | 2008/8/27 15:14 |
| Estimating power consumed by a SRAM for each input vector. Dear all, I have the layout of the RAM and I will be simulating the circuit by passing input vector stream to the RAM. I would like to know how can I estimate the power consumed by the RAM for each... |
hualeyan | 5/2 | 2008/8/27 15:17 |
| Synthesis Tools for Mixed-Signal ICs: Progress on Frontend hi everyone, I need this paper urgently. "Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies" 33rd Annual Conference on Design Automation (DAC'96) pp. ... |
398338 | 4/2 | 2008/8/27 14:46 |
| Store sample data in Cadence I would like to sample a digital signal at each clock and to save it in a file for analyzing it in Matlab. Does a simple model exists in a standard lib or do I have to make a hdl model? |
edu | 4/5 | 2008/8/27 15:31 |
| How to define sampling capacitance in pipeline ADC? Hi, my friends please help As we know, sampling capacitance will induce noise. The value is (kt/c). How can i accurately define the least value of the sampling capacitance in THA? From SNR constrai... |
yvling | 15/3 | 2008/8/27 15:28 |
| What's this? Hi all, How to draw this layer? ex. POLY NOT Contact I got this from the LVS rules file. Someone please shed some light here. Thanks in advance. -no_mad |
ai8957382 | 3/4 | 2008/8/27 14:55 |
| Bloodshed c I am using Bloodshed c . Does anybody know: 1) If exe files can be created from Bloodshed c . 2) Can you wirte a simple program (for example Hello World) and write the instructions of how t... |
yutcxa | 5/1 | 2008/8/27 14:39 |
| SCL NAND HI, I have to design a scl nand and different SCL (source coupled logic) latched.. on .35um technology. the only thing i dont know any thing about it and on web i cant find any schematics or deta... |
398338 | 4/3 | 2008/8/27 14:38 |
| ADC layout I just found an ADC layout, is there anyone know why they put six rings between pads and the core? Thanks in advance. |
fujun2013 | 4/1 | 2008/8/27 14:32 |
| ASSURA VS CALIBRE VS DIVA Which is the best tool for verification,userfriendly for layout a)Assura. b)Calibre. c)Diva vote for ur best verfication tool. |
ybyygu | 11/23 | 2008/8/27 14:29 |
| how to get imput impedence waveform from Cadence I simulated a single NMOS transistor and got the waveforms from transient and AC analyses. But I am not sure how can I get input/output impedence waveforms from Cadence by using calculator. say for... |
nnxd | 5/4 | 2008/8/27 15:44 |
| which tools are better for verification (DRC ,LVS and RCX) which are better ASSURA or DRACULA or DIVA or CALIBRE or HERCULUS? Is there using DRACULA in companies? |
hgping | 6/4 | 2008/8/27 14:34 |
| about mix-signal simulation hi can someone tell me wich software is more useful for the simulatin of mix-signal circuits ? THX. |
btcdtc | 4/7 | 2008/8/27 14:43 |
| Over temperature Protection circuit. Hi Experts!!! Please give me a advice or other solution for below circuits. It's a over temperature protection circuits. Thanks!!! |
naoge | 4/12 | 2008/8/27 15:35 |
| multiple vias Hi, I'm a beginner in layout designing. I wanted to know why do we use multiple vias n contacts instead of a single via and contact.. |
stgod | 6/13 | 2008/8/27 14:52 |
| A/D bit rate,max IF sampling and Nyquist criteria question Hi all, What are the differences between bit rate and Max IF sampling in A/D? And how it is settle with the Nyquist criteria? Because I have seen a TI ADS5545 with 170Msps bit rate and 500MHz I... |
addxjyx | 5/9 | 2008/8/27 14:42 |
| Region Defination of BJT in cadence? Hi Dude, Anyone knows the region defination of BJT in cadence, just like "0 cutoff 1 linear 2 saturation 3 subthreshold 4 breakdown" for mos ? I could not find it anywhere. THx in advance! Be... |
pdang | 3/4 | 2008/8/27 14:35 |
| Noise Figure simulation using HspiceRF Hi, there: I am using HspiceRF to simulate a LNA, I just want to know whether or not does the output port impedance affect the NF calculation, or is the output port impedance specified in port statem... |
fusarium | 17/2 | 2008/8/27 14:53 |
| paper problem Dear all: The attached figure is from a paper. (Y. Moon, et al., "a quad 0.6-3.2 gb/s/channel interface-free cmos transceiver for backplane serial link," JSSC, vol 39, pp. 795-803, 2004) In th... |
398338 | 13/4 | 2008/8/27 14:47 |
| Input bias of transconductor Since a gm cell works in an open loop fashion, how is the input bias determined? Should the gm cell include an internal biasing circuit to set the input point voltage? However, from some gm-c filter ... |
saigu | 4/3 | 2008/8/27 15:12 |
| What are the Pulse parameters? Hi ,,, In my design i use pulse as input to my ckt , so what are the pulse parameters should i use for pulse simulation (falling t, raising t, delay t, etc) to get close results. thanks |
nnxd | 16/12 | 2008/8/27 14:54 |
| Using fingers in Hspice If we use fingering in layout the Drain/source cap is reduced by that factor. Is it the same case when we use Hspice. Imagine I set M=2 in hspice which means I am using a finger of two, will hspice co... |
chdd | 5/3 | 2008/8/27 15:38 |
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