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| Homepage >> RFEDA FORUM >> Analog IC Design & Layout | [View In Forum] [New Post In This Forum] | ||
| Title | Author | Views/Replies | Posted at |
 how does one capacitor charge another capacitor?C1 has been connected to a voltage source V1 for a long time,at time 0,the switches switch the connection from V1 to C2,i.e. V1 is cutoff,and the two capacitor are parallel connected,what is the volta... |
lassa | 12/8 | 2008/8/27 14:46 |
| Help: Can anybody give me 0.25um or 0.35um cmos technology Can anybody give me 0.25um or 0.35um cmos technology parameters ,Thanks |
fusarium | 4/12 | 2008/8/27 15:16 |
| what do i need for autorouting of analog circuit ??? what do i need for auto-routing of analog circuit ??? are ic5141, icc11241 and pdk enough ??? if not , what else do i need ??? thank you ! |
ct731 | 5/8 | 2008/8/27 14:48 |
| Micro current source If it is possible to realize a micro current source with CMOS technology? It's AC output current is several uA, and it's DC output current is approximately equal to zero(indeed,a positive value to ma... |
wyslnhhh56 | 4/1 | 2008/8/27 15:41 |
| CMOS logic gates and digital circuits in 0.18u process Hello, In my design there is the Digital control part, so I want to ask about digital design in CMOS 0.18u process. I'm now using Cadence 5141. |
spacebac | 5/17 | 2008/8/27 14:51 |
| IC Design Interview Hi all, Can anyone share some examples of IC design interview Q&A? Please give the example questions relate to R,L,C, CMOS, layout and digital. many thanks. |
btcdtc | 5/4 | 2008/8/27 14:58 |
| Laker Tech file ? Hi , anybody familiar with tech file format of Laker tool ? Can u tell me the difference between LayoutLayerRule section adn LayoutVerifyRule Section ? thanks bye |
rickli | 5/7 | 2008/8/27 14:49 |
| question about charge pump voltage doubler bulk voltage Just as described in the pic: My question is how to determine the bulk(S3,S4) voltage? I want to get a regulated voltage vout:vin |
hualeyan | 6/2 | 2008/8/27 15:15 |
| Scope of IC design in Australia Hi what is the scope of IC design (mixed signal design) in Australia... I am a permanent resident of Australia and having a experience of 2 yrs in Mixed signal design and digital design. Would lik... |
chdd | 14/4 | 2008/8/27 15:29 |
| Problem with capturing Plot in cadence Hi all When I trying to save a plot output from simulation in cadence tools as an image i have this problem. I save the plot using : File>>save as image>>OK |
hualeyan | 3/2 | 2008/8/27 14:50 |
| pathing difficulties in common centroid structure Hi, friends. I am trying to layout a pair of differential nmos, which are used in high-speed amplifier. The inputs terminals are their gate. And their layout are like follows: ... |
fujun2013 | 3/13 | 2008/8/27 15:30 |
| Matlab and spectre simulation Hi, all I heard somebody said that it's feasible to execute the simulation program such as "spectre" in MATLAB. Anybody knows how to do this? or is it impossible? |
spacebac | 4/2 | 2008/8/27 14:48 |
| tt, ff, ss process corners i am simulating my amplifier for different process corners...i've noticed for different process corners simulation the current consumption is different !!! Can anyone tell me.....why the current co... |
lassa | 3/4 | 2008/8/27 15:15 |
| Books wanted!!! Any books on Data Converter recommended? Are they available in this forum? Thanks in advance! |
yutcxa | 3/2 | 2008/8/27 15:18 |
| why do we use poly to connect poly why do we use poly to connect poly |
anuo2008 | 3/5 | 2008/8/27 14:42 |
| how to calculate output res based on simulated op point? dear guys, how to calculate the output resistance based on the saved op point? i found that in spectre, the "ron" shown in the table of op point did not equal to gain/gm. it is so weired. how is... |
dongyea | 5/2 | 2008/8/27 15:36 |
| current source hi I want to make simple current source with two transistor do power transistors do it without problem I dont need precision |
hualeyan | 3/6 | 2008/8/27 15:08 |
| Cadence ADE Mixed-Signal simulation problem I use Cadence Analog Design Environment to simulate a mixed-signal system (Verilog, verilog-A, schematic, spectre models). But there is sth wrong in the interface between a verilog block and voltage s... |
z315 | 4/3 | 2008/8/27 15:32 |
| BSIM3 noise model flag, noimod, and PNOISE Hi there Do you know where I can find noise model flag, noimod, in my technology mode file (*.scs) for spectre ? Since I would like to whether noimod=1 or others in order to check my PNOISE simu... |
chdd | 6/1 | 2008/8/27 15:33 |
| Help:synchronous of data and clock in mixed signal systems? In mixed signal systems, how to ensure the syncrhonous in exchanging data in the interface of Digital and Analog? e.g. the output data of ADC shoud be sent to digital, then I should send a synchronous... |
anuo2008 | 2/3 | 2008/8/27 15:32 |
| AC Analysis in Cadence Hello, Iam fairly new to cadence and I was trying to do get a frequency response of a Common Source NMOS Amplifier in Cadence. I used a resistive load of 10M. I biased it at the gate with a DC so... |
naoge | 4/4 | 2008/8/27 15:42 |
| Monte Carlo Mismatch Analysis Help I am running the Monte Carlo mismatch analysis on a Miller OTA from -3 sigma to 3 sigma. This kills my performance for the Miller OTA on some random patterns. Basically the node labelled Y in ... |
ken7976 | 4/4 | 2008/8/27 15:33 |
| What is CMFB ?? I would like to know what CMFB is all about why and how it is acheived. Thank you in advance. |
lassa | 5/6 | 2008/8/27 14:38 |
| cadence vs tanner L-edit which one is better or more user friendly?? |
ken7976 | 72/30 | 2008/8/27 15:27 |
| Function properties window problem in Cadence 5.033 Hi all, I just installed Cadence 5.033 on my system. In Virtuoso Schematic and Layout Composer when I press "m" or select move function from menu, the function works but I cannot see its properties d... |
stgod | 5/5 | 2008/8/27 15:38 |
| no dc path to ground from node 0:2 Hello, I meet this kind of error a lot. Usually I can find the float point. but I never know where is 0:2. How can I find a 'node' called 0:2 in Cadence? Thanks. |
rickli | 4/5 | 2008/8/27 15:37 |
| Gate Length In the Layout of output pad driver transistors, why is the gate length often lenthened at both ends of the gate? |
spacebac | 5/1 | 2008/8/27 15:23 |
| PSRR OF THE BIAS Many people try hard to enhance tbe PSRR of eh bias circuit, but they all focus on the PSRR that is VDD. But much of BGR take the GND as refrence , if the circuit is in a bad surroundings, such as la... |
fujun2013 | 6/3 | 2008/8/27 14:50 |
| where to find some tutorial to Where can I find some cadence tutorial so that I can follow the step to do some excercise to design a complete analog IC(From schematic to layout)? |
398338 | 3/2 | 2008/8/27 15:38 |
| Resistor Problem ! Hello, I'm a new hand of IC design, I want to ask the question is, Can I lay a 40Kohm resistor ??? Is it possible/suitable ? Because I find that the process sheet resistance of Poly is 7.5 ohm/squ... |
saigu | 4/9 | 2008/8/27 15:39 |
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