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| Title | Author | Views/Replies | Posted at |
 Common mode feedback circuithi everyone could u please tell me the design criteria in CMFB circuit for folded cascode, how to choose the circuit topology. is the current flowing in it is same as that of tail current source. re... |
398338 | 4/1 | 2008/8/27 15:37 |
| How do you deal with patents when you are designing a chip? Do you search patents for each subblock and make sure these blocks do not violate other guy's patents? Or just do whatever you want to use and hope nobody else will know? Please experienced desi... |
gao51755775 | 5/14 | 2008/8/27 15:00 |
| function of the capacitance Hi,everyone! I can not understand the function of the two capacitances in the circuit below the two transistors are the loads of a differential follower and the base of the two transistors is a con... |
bubulu | 11/7 | 2008/8/27 14:29 |
| How to design a current reference with zero TC? where can find a current reference circuit with zero TC? I read some papers. The method is to find the sum of PTAT current and invert PTAT current. And Is there any other method? |
wyslnhhh56 | 5/12 | 2008/8/27 15:35 |
| How to decide the value of sample capacitor Hi All: If I design a sample and hold circuit for an A/D converter, for example, the A/D converter has 10 bit resolution. How can I choose the proper value for the sample capacitor. Any... |
saigu | 2/5 | 2008/8/27 15:36 |
| need a paper,help me hi all:i need a paper: "Effects of the op amp finite Gain and. Bandwidth on the performance of Switched-Capacitor",ken.martin,1981. regards |
nnxd | 4/1 | 2008/8/27 15:07 |
| Pcell generation using skill .. plz suggest Hi, I have generated transistor pcell using GUI/tool ("compile to pcell" option). I m able to set width/lenght/no of fingers.. . Now normally when we instantiate pcell , Instance name gets ... |
naoge | 4/6 | 2008/8/27 14:38 |
| Corner Analysis Is there a way to include matching into corner analysis (in spectre / MMSIM60)? In my case I have two (!!!) differential pairs which should match - but during corner anlysis for the "wp-case" the ... |
gao51755775 | 7/2 | 2008/8/27 14:46 |
| How do I specify an external input stimulus file in Cadence? Hi, I'm new to cadence. But I have been tinkering with it for some time now and I am comfortable working with the Analog Design Environment using specterS. My question is: Can I specify an externa... |
addxjyx | 4/5 | 2008/8/27 15:19 |
| Basic MOS structure question I want to ask, in a MOS structure. Why thereis a band-bending in the interface of Oxide and Semicondutor. In the meanwhile,why the fermi level remain straight across all the three material. Just l... |
fusarium | 6/9 | 2008/8/27 15:36 |
| power analog IC reference book Do you know any good book about power analog IC using cmos, bipolar or bicmos process? Thanks. |
htc2498 | 4/1 | 2008/8/27 15:26 |
| LDO internal zero hello I need a circuit which will introduce an internal zero in LDO's frequency response. I will also use an external capacitor but i could use lower esr then. I have found one solution, but it ... |
hualeyan | 4/6 | 2008/8/27 15:10 |
| about PLL loop bandwidth When mentioned that "loop bandwidth should exceed 10% of reference frequency", here does "loop bandwidth" stand for the bandwidth of OPEN Loop transfer function or Closed loop transfer function....or... |
knoxville | 4/5 | 2008/8/27 14:41 |
| Opamp Distortion: simulated Vs. measured results? Opamp worked in the frequency bands: <100MHz, 0.25祄 CMOS technology. what about the gap of distortion performance (HD3, or IM3) between the simulated and measured results? someone has experience? ... |
ken7976 | 5/1 | 2008/8/27 15:09 |
| ESD What is ESD and how can we do ESD protection in Layouts |
bubulu | 4/2 | 2008/8/27 15:06 |
| help! about this gain-boosting OTA HI: I designed a OTA with telescopic gain-boosting architecture, the main OTA has a DC-gain of 50dB, and UGB 450MHz, the auxiliary amp are 61dB 308MHz, and 69dB 314MHz, respectively. But, combine... |
naoge | 5/11 | 2008/8/27 14:37 |
| why some layers missed in the extracted view ? why some layers missed in the extracted view ? i put a MOS with it's d and s connected to ground, then layout, drc, lvs, and finally extracted. but some layers missed in the extracted view of av... |
mxg330 | 4/13 | 2008/8/27 14:40 |
| About Bandgap I designed a CMOS bandgap, in which there is an op amp. When I measured the bandgap's output, I found this value changes from chip to chip. So what could be the reason causing this change. Thanks! |
booksir | 5/11 | 2008/8/27 14:45 |
| How to choose a process for a design Hi All, Choise of a process would depend on what all factors? I am sure the what we are designing would be most basic, along with electrical parameters for that design. Assume if we need to desig... |
yutcxa | 17/8 | 2008/8/27 15:26 |
| closed loop fully OPM problem I design a cascode_fully opm with cmfb, in the closed loop condition with gain equal to 1, the input is a sinewave of 1v, so the output signal should be 1v , for the sample reason that the gain=1, how... |
z4120356 | 5/4 | 2008/8/27 14:49 |
| AMI 0.5um Bipolar model file needed. Can you give me the AMI 0.5um Bipolar model file as well as the definition (physical structure)? Thanks. |
nnxd | 4/1 | 2008/8/27 15:06 |
| op amp layout Hi, I have a question regarding op amp layout. Generally, what is the critical requirement for the layout? I heard that direction of the current not that critical nowadays because the way they do th... |
mxg330 | 6/5 | 2008/8/27 15:44 |
| Questions about AGC and ADC in GPS systems. Hi, I have some questions about AGC and ADC in GPS systems. In GPS systems, 1. how long response time could tbe AGC loop have? 2. should there be a differential-to-single-ended amplifier be... |
nnxd | 3/1 | 2008/8/27 14:56 |
| bandgap how to design a low supply voltage bandgap that can work under the 1.5V supply voltage? |
wy830115 | 6/8 | 2008/8/27 14:50 |
| design the LC VCO Can someone why the Q of the inductor in the technics of TSMC .18u is so small ? thanks! |
pdang | 4/15 | 2008/8/27 15:02 |
| Layout in analog ic design Hiiii i m very new in layouting of analog ic's ? I have one book The art of analog layout by ALLEN HASTING but i m not getting more about the finger dividing of a large width transistor. |
scuzt | 5/8 | 2008/8/27 14:35 |
| Please give me suggestions for choosing OPAMP buffer My spec is shown below: Vcc up to 16V Rail to Rail for both input and output 3db bandwidth > 15MHz Out put current " 50mA, Can anyone tell me which vendor provide? |
stgod | 4/3 | 2008/8/27 14:47 |
| about chopper comparator anybody know about chopper comparator? Thank you! |
bubulu | 11/1 | 2008/8/27 15:45 |
| [Need Help]analog circuit Hi everyone, I want to know the procedure "residue amplification",say, (2Vin-dVref) in MDAC(multiplying DAC). Attatched file is "A 10-b 15-MHz CMOS Recycling Two-Step A/D Converter, by BS Song... |
398338 | 13/1 | 2008/8/27 15:46 |
| The psot-sim of MOM-cap DearAll : Does any other have good to extract the MOM-cap (cap fringer) , Now I design 0.18um MOM-cap with VIA. I use calibre to do extraction, But I found the command files mo define VIA-... |
fujun2013 | 5/3 | 2008/8/27 14:44 |
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