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| Title | Author | Views/Replies | Posted at |
 How to suppress distortion of the SC sampling switches? HelpHi all, To suppress the distortion of the sampling switches that needed to pass 500MHz bandwidth signal, some techniques has been done it before: 1) Increase the transistor size to reduce the on... |
dongyea | 5/10 | 2008/8/27 15:22 |
| Scope of IC design in Australia Hi what is the scope of IC design (mixed signal design) in Australia... I am a permanent resident of Australia and having a experience of 2 yrs in Mixed signal design and digital design. Would lik... |
chdd | 12/3 | 2008/8/27 15:29 |
| Help me to find this old paper? L. K. J. Vandamme and H. M. M. de Werd, “. 1/f. noise model for. MOST’s biased in nonohmic region,” Solid State Electron, vol. 23, pp. 325–329, 1980 Thanks very much! |
ct731 | 6/1 | 2008/8/27 14:50 |
| what difference in Analog(MIXED) and digital technology lib. Such as TSMC ,Both have mos and res instance.what is difference? Thanks. |
booksir | 7/3 | 2008/8/27 14:40 |
| Sub Threshold Models in TSMC 0.13 Dear All, Does anyone know if TSMC 0.13um design kit has accurate modelling of the subthreshold region? Regards, ElBadry |
naoge | 5/8 | 2008/8/27 14:45 |
| mentor graphics micro vision download i've completed reg also. sele ted educational version. finding difficulty in downloading mentor graphics microvison. can anyone help me to solve this problem or other link 4 the same. |
scuzt | 5/1 | 2008/8/27 14:45 |
| how to add a resistor model from a model card AA hello there i am using cadence IC 5.141 and i want to add the tech. parameters to the resistors in my design i already have a TSMC 0.18 model card (.scs) whcich contains resistor corner model , b... |
fujun2013 | 4/6 | 2008/8/27 15:20 |
| wire quesiton Dear all, If I have a long metal wire,I will consider delay time question. Maybe I will add inverter to improve delay time. Besides this method, does everyone have anothor method? Thanks. |
pdang | 10/6 | 2008/8/27 15:32 |
| What is the relationship between S21 and Ga? I guess the |S21|*|S21| should be the same with Ga? Because S21 measures the ratio of the available power stream flowing into the load to the available power stream flowing from the source. Is this... |
ct731 | 4/3 | 2008/8/27 14:38 |
| PLL question, need experienced guys help! here is a difficult question about PLL design. assume i have 32.768k ref clock, how i can design a analog PLL to supply LO for FM band 87-108MHZ? to design 2X or 4X LO for PLL frequency, how to choo... |
netlgc | 6/7 | 2008/8/27 15:10 |
| Need lecture :EE273 - Digital Systems Engineering EE273 - Digital Systems Engineering http://eeclass.stanford.edu/ee273/ |
stgod | 14/1 | 2008/8/27 14:29 |
| how can i get the spice parameters of BJT. I am a student.I want to study bandgap reference.I can get CMOS spice parameters from MOSIS.com.But how can i get parameters of lateral BJT which are compatible with CMOS process? |
ken7976 | 7/4 | 2008/8/27 15:28 |
| Problem with simulating dual path loop filter in Spectrerf I've designed a dual path loop filter (as attached) and plug it in my linear model in Spectrarf but an convergence error occur during simulation. Can anyone help? Thanks |
stgod | 8/2 | 2008/8/27 14:30 |
| implement an on-chip band-pass filter with fcenter=200MHz How can a band-pass filter with fcenter=200MHz implemented on chip? The spec of the bpf is loose: bandwidth: 100MHz; gain can be less than 0dB; on-chip inductor is not available. Any suggestions? Than... |
zunwang | 8/2 | 2008/8/27 15:27 |
| Switch cap circuit , Noise analysis Dear all : Does have have good paper or thesis about the topic. How do u model it ? ANy matlab code or other method . Thanks |
ai8957382 | 6/6 | 2008/8/27 14:47 |
| How to create a 2E3B2C device in Cadance? Hi, Just wanna to ask a dumb question: How to create a npn1 device with 2 base, 2 collector and 1 emitter stripe in Cadance? And, how to create a npn1 device with 2 collector, 3 base and 2 em... |
stgod | 5/2 | 2008/8/27 14:54 |
| what's the disadvantage of this CMFB circuit? Please check the attached figure... Most op-amps use a pair of identical resistors or switched-cap for CMFB circuit; what's the drawback of the attached alternative form CMFB circuit without resist... |
nnxd | 5/11 | 2008/8/27 15:25 |
| bandgap design, 3v supply using bjt anyone can help me? i need to design a bandgap having a 3v supply using bjt. any paper or information that i can read up? or anyone have any suggestion? thx in advance |
edu | 7/2 | 2008/8/27 15:14 |
| AR1000 (Airoha) Dear All : Does anyone have AR1000 (Airoha) specific ? Thanks |
398338 | 14/1 | 2008/8/27 14:36 |
| LVS question ?? while i was doing LVS using (Assura) ,i finshed fixing all the errors and this message appears to me : Unknown LVS error found see test.cls file for details. what does it mean ??? and i ope... |
booksir | 10/4 | 2008/8/27 15:32 |
| Virtuoso Required... Can I get Virtuoso from somewhere, Trial version Or some Other Tool for layout design. My purpose is purrely academic and not software piracy,as I am an student. So please provide me this tool. Ple... |
spacebac | 9/5 | 2008/8/27 15:45 |
| Level-shifter papers? I was googling about level-shifter papers and I saw that most of the designs are under patent protection, can someone explain the reason? |
z4120356 | 5/4 | 2008/8/27 15:00 |
| I need the CMOS circuit of the CAN bus transceiver! Can someone offer the CMOS circuit of the CAN bus transceiver, such as PCA82C250 to me? Thank you! |
wyslnhhh56 | 3/1 | 2008/8/27 15:08 |
| ESD Layout Hello, Can anyone give me the reason why we put an Boron implant / Salicide blockage layer on ESD structures. Also why do we maintain more spacing between diffusion contacts and Active poly? P... |
spacebac | 8/3 | 2008/8/27 14:31 |
| LDO design What is Line and Load regulation ? why do we need to take care on it on circuit design ? For LDO design, How do we measure them ? I have read a paper on LDO design such that it is "stable on an... |
398338 | 4/6 | 2008/8/27 14:47 |
| How to design 3rd order RC filter I want 4kHz LPF, I design R=780K, C=10pF, and 3 same RC in series, the -3dB is about 4KHz, is the design right? if right but the size is too big to integrate in IC, can anyone give me some instructi... |
yvling | 9/3 | 2008/8/27 14:49 |
| Bandgap Reference : Ground current Hi All, Can someone tell me where can I get references for a bandgap reference ckt with the ground current < 1uA ? TIA Raduga |
saigu | 18/11 | 2008/8/27 14:32 |
| 1553 Output driver symmetry I'm working on the developement of a a MIL-1553 transmitter. As required by the standard, the output signal, which is differential, must be nearly perfectly symmetric. This is to reduce any residua... |
mxg330 | 8/1 | 2008/8/27 15:06 |
| What define Cgb Cdb in hspice simulation? Help! The Cgb and Cdb is defined by layout diffusion size which is AD, PD, AS, PS. But I am confused that when I simulate using level 49 model the Cgb and Cdb exist without writing AD, PD, AS, PS parameter.... |
chdd | 9/4 | 2008/8/27 14:45 |
| explain these term of verilog what is the difference between the below given keyword. 1) $strob 2) $display 3) $monitor 4) #0 5) $stop 6)$finish How the are diffrent with each other? |
zunwang | 5/3 | 2008/8/27 14:49 |
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