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| Homepage >> RFEDA FORUM >> PLD, SPLD, GAL, CPLD, FPGA Design | [View In Forum] [New Post In This Forum] | ||
| Title | Author | Views/Replies | Posted at |
 [SOLVED] ISE WebPACK 8.1i .msk missingHello, I had installed in my system ISE WebPACK 8.1i All goes well, until when running iMPACT to program the FPGA and PROM. 1) FPGA programming without VERIFY check box runs fine .... |
z4120356 | 4/1 | 2008/8/28 06:26 |
| Any Doc. or Schematic about PC download design file to FPGA? Anybody have this? Thanks |
fujun2013 | 4/2 | 2008/8/28 07:04 |
| a problem of modelsim # Reading d:/ise6.1/tcl/vsim/pref.tcl # do ff.fdo # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 # -- Load... |
hualeyan | 4/2 | 2008/8/28 06:53 |
| Fastest HDL simulator? Which is the fastest HDL simulator you have you used? Out of the ones I've tried: ModelSim, VCS and IUS (LDV), I would say VCS is the fastest. Although I use ModelSim mostly because that is what is ... |
spacebac | 8/3 | 2008/8/28 06:42 |
| how to split bus going to different blocks? I have 3 blocks one with output second block with input third block with input please help, I want to connect the output pin to second and third block however how to do it,..... |
fujun2013 | 8/7 | 2008/8/28 06:23 |
| Connecting Symbols in a .bdf file in qu(at)rtus II Hello everyone, I have designed two separate .bdf files and then made their corresponding symbols. I have then created a new .bdf file and then trying to put all these symbols and connect ... |
ken7976 | 4/3 | 2008/8/28 06:19 |
| info about channel estimation algorithm imp on fpga if anyone has any info about this channel estimation for wcdma and its implementation on fpgas plz share it, b/c i have taken it as my final project. |
hgping | 23/2 | 2008/8/28 06:54 |
| help spartan 3 starter kit: reset signal the push buttons on starter kit are not debounced, how to generate reset signal for processor duration 4-5 clk (20MHz)... |
ken7976 | 5/4 | 2008/8/28 06:49 |
| IP protect software? How to creat a software IP for RF? I hope it is protected and send to customer evaluation without lose its design detail? |
netlgc | 4/2 | 2008/8/28 07:08 |
| how can i execute delay time?? How can I make simulation for inertial delay and transport delay? I tried to execute these examples Library ieee; Use ieee.std_logic_1164.all; Entity buf is Port (a : in std_logic; ... |
ai8957382 | 4/3 | 2008/8/28 06:18 |
| Small depth Async FIFO Can anyone did small depth (two or four) asyncronous FIFO? I am facing problem in such a design. If anyone has the code plz upload. Thanks |
hualeyan | 6/5 | 2008/8/28 06:33 |
| ise 8.1 hi all i want to open with ise 7.1 a project developed in vhdl with ise 8.1 It s possible ? Thank s in advance |
z315 | 3/3 | 2008/8/28 06:37 |
| Using internal RAM with Spartan 3E - VGA data Hi there. I've been working with my Xilinx Spartan-3E starter kit for a few months now and have learned the foundations. Currently I'm trying to figure out memory so I can store simple data for VGA . ... |
scuzt | 3/5 | 2008/8/28 06:22 |
| why 9 values Hi, Why we have 9 values in Std_logic, as in real world only 3 of them exits. '1', '0' and 'Z'. Thakk you |
chdd | 5/2 | 2008/8/28 06:14 |
| an error when running ISE. THE ERROR is ERROR:PhysDesignRules:368 - The signal |
fujun2013 | 4/2 | 2008/8/28 06:18 |
| Dinamic or refresh - visualization Hey friends... I need help with the code in vhdl for dinamic visualization, thanks. |
mxg330 | 3/1 | 2008/8/28 06:26 |
| how to delay the signal? Hi everyone, I use @ltera MAXII CPLD for my project. I program it using qu(at)rtus II software and VHDL language. With CPLD I control switches using one global clock signal. For one switch, I want ... |
pdang | 4/13 | 2008/8/28 06:14 |
| Task in Test Bench..... can anyone post an example along with the test bench.......using TASK Thanks a lot........ |
zunwang | 4/2 | 2008/8/28 06:33 |
| soft output viterbi decoder hello; i am a student and i need in my project the vhdl code of the soft output viterbi decoder ,please help me as soon as possible. it would be a valuble suggestion from you. thanks and regards... |
ct731 | 13/2 | 2008/8/28 06:27 |
| Verilog newbie problem Hi I am using QuartusII and it is not happy with the Verilog code below. It gives this error: Error: Can't resolve multiple constant drivers for net "BUSY" I would appreciate it if someone co... |
fujun2013 | 8/5 | 2008/8/28 06:41 |
| C code for kernighan-lin algorithm(partitioning) hi, i want C code for kernighan-lin algorithm used in partitioning,any one who have it can please send to me. with regards |
gao51755775 | 3/3 | 2008/8/28 06:14 |
| which tool support XC5204 which tool supports XC5204 from X!l!nx ?? I can't find it in ISE 6 or 5 , even the foundation 4.1 doesnot support it ! |
addxjyx | 6/5 | 2008/8/28 06:55 |
| DDS Help anyone please help . tell me the step to come out with DDS 120 MHZ 8 bit please help |
bubulu | 15/30 | 2008/8/28 06:14 |
| How to implement the primitive HI all The primitive tranif0 and tranif1 are not support by Xilinx for synthesable design ,but my design needed to implement the function of primitive "tranif0 or tranif1 " for ex... |
bubulu | 15/3 | 2008/8/28 06:47 |
| frequency generator in VHDL Are there any VHDL code and methods examples of a frequency generator design? |
scuzt | 3/3 | 2008/8/28 06:44 |
| any sasken placement papers i had an saken , can any body sent me model of paper ,i'm doing m.tech in vlsi |
wyslnhhh56 | 3/2 | 2008/8/28 06:24 |
| Nu Horizona Spartan Board Hi All, I need to put my design to NU Horizons Spartan 3 Board. I am using webpack 6.3i and I can put my design into the board without any problem but every time I disconnected adaptor from the b... |
mxg330 | 4/4 | 2008/8/28 06:59 |
| @ltera 7K / 3K diff hi, What are the main different between @ltera 7K and 3K CPLD thx |
398338 | 5/9 | 2008/8/28 07:09 |
| Needed help.. regard my final year project Hi anyone, Could you please provide any project titles. i had no idea about what to select as my final year project. If possible please tell me where could i find or where i could gather the know... |
zunwang | 5/1 | 2008/8/28 06:06 |
| .jam or .svf for max7064? Dear All, how to generate a .jam or .svf with QII for the max7064S for example. I supposed that should be easy but I don't find the way. I have generated a .pof file. My idea is to generate a .ja... |
zunwang | 3/1 | 2008/8/28 06:56 |
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