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| Homepage >> RFEDA FORUM >> PLD, SPLD, GAL, CPLD, FPGA Design | [View In Forum] [New Post In This Forum] | ||
| Title | Author | Views/Replies | Posted at |
 Globle Clock in xilinx fpgaWhen I should use the globle Clock and DCM resourse,if the globle clock and DCM can improve the freqeuncy,The DCM can make 0 clock skew,but i think sometimes it make the bad effect,e.gthe data path de... |
hualeyan | 2/3 | 2008/8/28 06:52 |
| HI I am looking for a way to implement a simple BPSK modulator and demodulator in VHDL, but could not find any prewritten code to learn from on this topic. Can someone help me in regarding to this. ... |
rickli | 2/1 | 2008/8/28 06:39 |
| question about GMSK demodulation Hi all, when I sample the down-converted I/Q signals I get cosφ and sinφ,how to calculate the metrics of viterbi decoder? I think if I could get the Δφ over one symbol period th... |
z315 | 4/1 | 2008/8/28 06:29 |
| FFT 32 Point,32 bit input in fpga i want to know,how can i implement FFT 32 Point,32 bit input in fpga? any code in vhdl or web site or information about this matter is usefull. i can change inpunt bit to 8 bit ......... ... |
stgod | 3/4 | 2008/8/28 06:20 |
| some question about FPGA implementation by impact hi, Please answer my questions: 1- In figures 2-9 and B-1 of pac.pdf it is determined that we must connect the following pins to parallel port cable: cclk,DONE,DIN,PROG ... |
398338 | 3/1 | 2008/8/28 06:25 |
| Need some help ......... urgent HI, This is the query. The memory controller I need to design is for the CAN interface which is present on the FPGA. This would control the data transfers using the CAN interface, so there ... |
anuo2008 | 3/3 | 2008/8/28 06:06 |
| 68360 IP core Hi, does anybody has a proven 68360 IP core regards yam |
yvling | 3/4 | 2008/8/28 06:15 |
| What's the detail meaning of Thx! |
booksir | 18/4 | 2008/8/28 07:10 |
| Which starter kit ? Xilinx or @ltera ? Dear all , Which is better for a beginner to buy and start with ? Xilinx spartan3E starter kit : http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-U... |
zunwang | 3/1 | 2008/8/28 06:32 |
| vhdl: need help with PSW Hello, I am designing a General-Purpose Computer using vhdl. It contains Ram, MAR, MBR,...Register A with PSW, RegisterB with PSW... Right now, I am stuck at the Architecture entity, expeci... |
pdang | 3/1 | 2008/8/28 06:41 |
| FPGA BASIC ineed fpga guide so hat i have know how how to programm/design fpga so please help |
naoge | 3/5 | 2008/8/28 06:24 |
| REQ: METHODLOGIES ON COPYING CPLD Is there any methods of reading the contents of the CPLD with JTAG interface for @ltera Max class CPLDs. I have the byteblaster but unable to read the contents of the CPLD or is there any method. ... |
edu | 11/2 | 2008/8/28 07:09 |
| help! project due tomorrow! Trying to get this code to work...it runs fine on simvision..but when i transfer the code onto xilinx...i get problems.... |
htc2498 | 3/2 | 2008/8/28 06:46 |
| I have two problems about PLD. Please help me. thx hello! I have a pal22v10 in a circuit board. Can I read it's code to write another? And how can I coding Program into PLD. I use PALASM V1.5 before. But it must use in DOS. My system is WinXP. W... |
fusarium | 3/3 | 2008/8/28 07:08 |
| Need advices for buying an FPGA evaluation kit Hi guys, I want to buy an FPGA evaluation kit for studying. I have a little of money, so which kit I should buy ? Thanks, |
ct731 | 5/12 | 2008/8/28 06:39 |
| Wrong output while trying to use module repeatedly..Help! Code to find GCD... I want the code to find GCD by foll. method.. gcd(a_in,b_in,a_out,b_out) { if((b_in==0)||(b_in==1)) { a_out = a_in; b_out = b_in; } ... |
ct731 | 14/5 | 2008/8/28 06:10 |
| Pin configuration of Spartan 3 FPGA I am trying to build a microprocessor (a very small one) using Spartan 3 FPGA.I have been stuck for a long time on how to adress the pins of FPGA because i don't know where is C1,H3,K9 and other pins ... |
gao51755775 | 3/2 | 2008/8/28 06:57 |
| IPs in MHS file Hello all:) I am running a design in edk 6.1 version. and comes up with " Makefile cannot be saved to run process. Please ensure IPs in MHS file point to the right MPDs". The MHS doe... |
anuo2008 | 2/3 | 2008/8/28 06:19 |
| VHDL asynchrous circuit design and verification Dear All, Currently I am learning asynchrous circuit design and verification using VHDL. Is anybody have the examples about it that could help me to learn it? Thank you. .gaweng. |
ai8957382 | 3/1 | 2008/8/28 06:47 |
| Pulse los detection Hi, I need a pulse Los detection circuit, but I don't know how to implement it. The requirement is the block can give the alarm signal when no pulse(or rise edge) is found in given time. ... |
ken7976 | 2/5 | 2008/8/28 06:25 |
| Problem in using an opamp microwind and DSCH In DSCH schematic builder the opamp given in advanced tools has no Vsat and -Vsat pin.How does one know its value?or is there a default value? |
stgod | 4/1 | 2008/8/28 06:33 |
| Help with creating a scalable ISDN V.110 rate adaption core Hi, I'm trying to find information on how to create a scalable V.110 |
pdang | 2/1 | 2008/8/28 07:07 |
| memory in FPGA I am implementing a cache memory in FPGA. for that i need a memory of 16 bytes wide and 256 entries. I am implementing using VHDL. the problem is I want to download in FPGA. Is there any way t... |
hualeyan | 5/4 | 2008/8/28 06:43 |
| What's the time delay between seq stat using variable? Hi everybody!, consider this example, PROCESS(clk)IS VARIABLE a,b,c : STD_LOGIC; BEGIN IF RISING_EDGE(Clk) THEN a:= '1'; b:= NOT(a); c:= a OR b; END IF; END PROCESS; ... |
mxg330 | 2/13 | 2008/8/28 06:13 |
| VGA by verilog this is program of the VGA but to work please tell me the logical error ----------------------------------------------------------------------------- module ff (red_out,clk50,green_out,blue_out... |
wyslnhhh56 | 3/1 | 2008/8/28 06:41 |
| @ltera NIOS II I/O pins Hello, Can anyone please enlighten me about the I/O ports and pin on the NIOS II cyclone II board. Which pins should I use in case I need to use some Card like VGA or the cyprus USB card etc ... |
ai8957382 | 3/3 | 2008/8/28 06:40 |
| sata/pata who have mentor sata/pata ip core? plz PM me. |
z4120356 | 2/1 | 2008/8/28 06:35 |
| please help me for writing code in verilog for glcd I m using spartan 3 with 400k gate density and i m working with xilinx 9.1. Currently i m doing glcd having ks0108 controller i m finding very difficult to display a character in that glcd. please ... |
fujun2013 | 3/1 | 2008/8/28 06:08 |
| DVI, any help? Is there anybody with experience in this field? I have to develope a Digital Visual Interface receiver on an @ltera FPGA: I have to extract the RGB bits and the syncs. I'm also looking for DV... |
wyslnhhh56 | 5/4 | 2008/8/28 07:08 |
| help this verilog code! how pull code! always@(posedge s3 or posedge addpc); begin if(addpc) pc<=pctemp 1'b1; else begin pc<=13'b0000000000111;pctemp<=pctemp 1'b1;end end warning:pctemp isn't the always control envent! ... |
ct731 | 4/4 | 2008/8/28 06:47 |
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