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| Homepage >> RFEDA FORUM >> PLD, SPLD, GAL, CPLD, FPGA Design | [View In Forum] [New Post In This Forum] | ||
| Title | Author | Views/Replies | Posted at |
 Question about NCO.I saw ddt694's post, which mentioned: |
nnxd | 3/5 | 2008/8/28 06:50 |
| Simulation tool i'm seeking simulation tool that contain models of intel pentium II processor , and other chipset that relate to pentium II generation. |
wy830115 | 3/2 | 2008/8/28 06:42 |
| My MicroBlaze Soft-Processor clone is ready :) Finally this week end I'll launch my MicroBlaze clone for the very first time. I have been working very hard to create it. I hope not in vain. It synthesizes OK, just a final touch and it is goi... |
ybyygu | 3/14 | 2008/8/28 06:13 |
| PROBLEM: 74ls645 sim model? hello to all, I am trying to design a simulation model of an 74ls641 buffer. I have done and test it without success and I am a bit stuck. When I assert low not_g and set low dir I don't see the ... |
scuzt | 3/1 | 2008/8/28 07:02 |
| ModelSim Hello, I have downloaded and installed ModelSim SE 6.2b for Linux AMD64, because it's the simulator my teachers uses in my University to teach VHDL. The problem is that I cannot find licens... |
spacebac | 3/7 | 2008/8/28 06:35 |
| about mini project related to HDL hi i want mini project with details related to HDL language i.e either in VHDL or VERILOG with details. pls anyone help me its urgent |
naoge | 3/12 | 2008/8/28 06:25 |
| Need help - vhdl synplify How can I specify timing constraint in vhdl code as attributes? I don't want to use constraint file, I want to put them in vhdl code as attributes. I know how to do that for pin assignments. But I hav... |
ai8957382 | 4/1 | 2008/8/28 06:53 |
| SMC34C60 similar IP... I saw similar IP before time... |
z315 | 11/1 | 2008/8/28 07:10 |
| which download file should I use? I am doing a project using ARM9, I also want to use ARM9 and AMD 16 bit flash configuring FPGA(spartan3 xc3s400), I use serial slave mode, ARM9 get parallel data and I send it out by serial. but I don... |
fujun2013 | 3/4 | 2008/8/28 06:46 |
| Floating Point hello i m doing a search on floating point that can be implemented on a CPLD can anybody give me some extra useful links about this subject During my search i found this "Floating-Point HDL Packag... |
rickli | 4/2 | 2008/8/28 07:05 |
| Getting Error When downloading BIT file to FPGA hi i have created the .bit file.actually i dont want to download the file to flash memory. but i am getting error like Bitstream 98:There are ## difference impact 395 :there are ## d... |
zunwang | 3/2 | 2008/8/28 06:42 |
| Which Package to buy please i want to buy a good package to manage VHDL Projects please suggest a package to buy Xilinx ISE Mentor Graphics HDL Designer Aldec Active HDL @ltera qu(at)rtus or ... |
ybyygu | 3/4 | 2008/8/28 06:26 |
| ISE/EDK 6.3 vs 7.1... I tried both ISE/EDK 7.1 and 6.3 (all with latest service pack, but tested very quicly), and I'm having some problems with 7.1. For example, a Microblaze design that fit in 6.3 doesn't fit as tight i... |
fusarium | 4/3 | 2008/8/28 06:52 |
| help need for state machine outputs... Hi can anyone tell me do we need to clock the output assigned in a state machine before using it again in the state machine. it is like a feedback. so do we need to clk it or not. i want to... |
rickli | 2/6 | 2008/8/28 06:27 |
| help needed regarding final year project Salam , My name is Osama and Im entering in 7th semester BE Electronics from PAF-KIET. I want you people to please suggest me an FPGA based final year project with related schematics and... |
z315 | 3/3 | 2008/8/28 06:21 |
| on alterastratix 2 can we do this hi im using @ltera stratix 2 fpga which is having 4 enhanced plls and 8 faster plls. can i by using this fpga can i generate 980 Msps clock by using 2 mhz reference clock (sorry may any technic... |
netlgc | 12/2 | 2008/8/28 06:04 |
| how to write the below verilog code in vhdl b=a{1'b1}; a is a constant defined with 'define b is std_logic_vector for example a=4 then b=1111 |
anuo2008 | 11/4 | 2008/8/28 06:47 |
| Synplify vs leonardo? Hi all, I used synplify pro and leonardo spectrum to synthesis a design and every time i did that, for small pices of VHDL code or a large design, the maximum frequency evaluated by synplify w... |
stgod | 4/17 | 2008/8/28 07:02 |
| Comparison of VHDL, Verilog, and System verilog Its a very good whitepaper. http://www.model.com/resources/languagepaper/default.asp ~niks~ |
ybyygu | 4/3 | 2008/8/28 07:08 |
| Xilinx' ML403 Development Board I am thinking on buying a FPGA development board and i came across Xilinx' ML403 board and it seemed quite complete, with USB controller, LCD display, audio codec, video DAC, system ACE... But I ... |
ai8957382 | 4/7 | 2008/8/28 06:47 |
| How to Interface?? Hai.... Have any one can help me?? How to PC interface if i have 184 logic input?? Thy... |
addxjyx | 1/3 | 2008/8/28 06:56 |
| VHDL code portability Hello all, What is the best way to go about while doing VHDL coding for FPGA and not knowing the target device (atmel, actel, @ltera etc). Currently I try not to use vendor specific libraries, ma... |
hgping | 3/2 | 2008/8/28 07:03 |
| XST ERROR 1534 Hello, My VHDL code for Horizontal counter seems to compile without errors, however during the synthesizing process in ISE, it gives me the following error: ERROR:Xst:1534 - Sequential logic... |
fusarium | 3/5 | 2008/8/28 06:12 |
| DDR SDRAM with MicroBlaze Hi All i have Spartan-3E starter Kit i tried to connect the MicroBlaze with RS232, DDR SDRAM, and FLASH_16Mx8 using BSB wizard then i tried to generate the Bitstream but there are so... |
netlgc | 3/2 | 2008/8/28 06:08 |
| how to split bus going to different blocks? I have 3 blocks one with output second block with input third block with input please help, I want to connect the output pin to second and third block however how to do it,..... |
fujun2013 | 3/6 | 2008/8/28 06:23 |
| which cpld chip should be used hi, i want to learn cpld chip programming which chip i should go for? does following chips are ok XC9536xl-10PC44C(3.3) or XC9536-15PC44C(5V) priya |
lassa | 3/3 | 2008/8/28 06:52 |
| @ltera Dual-Clock FIFO Hi, I'm using the "dcfifo" mega function, from @ltera qu(at)rtus V 5.0, to design a 16550 UART in VHDL. The FIFO works fine. I use it in "Show-ahead synchronous FIFO mode”. - The f... |
wy830115 | 4/1 | 2008/8/28 06:46 |
| Switch Box in FPGA Do any body knows how to build the Switch Box(Routing) in FPGAs |
hgping | 4/1 | 2008/8/28 06:30 |
| guigelines for building a state diagram in FBGAdvantage hi all i need guidelines for building a state diagram using software FBGAdvantage . and , how can i convert this state diagram to a verilog code ? |
saigu | 3/2 | 2008/8/28 06:29 |
| Help for MaxplusII simulation I try to combine two group of VHDL project to one project, every individual project can be compliled and simulated OK, but the combined project cannot be simulated correctly, it can be compiled OK... |
398338 | 4/1 | 2008/8/28 07:02 |
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