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| Homepage >> RFEDA FORUM >> PLD, SPLD, GAL, CPLD, FPGA Design | [View In Forum] [New Post In This Forum] | ||
| Title | Author | Views/Replies | Posted at |
 Good free Pic core and tutorialI'm looking for a good free pic core and tutorial Xilinx FPGA. If anyone knows were can I get a ISE project with a Pic core can you send me the adresse or the project. Thank for your help. |
netlgc | 4/5 | 2008/8/28 07:07 |
| Good Morning everyone !! simply Error . help to solve Error: (vcom-11) Could not find work.poller. can anyone tell me . what is it about . my file cant link together . i cant run modelsim Help~~ |
lassa | 5/3 | 2008/8/28 06:19 |
| Anybody explain FIFO functionality as well its working...... Hi everyone.......... Anybody explain FIFO functionality as well its working...... thanks |
wy830115 | 3/3 | 2008/8/28 06:27 |
| Xilinx Webpack Hi I have the Xilinx Webpack. Is it possible to use it to instantiate the MicroBlaze uP or do you need the full version? We will be starting a new project - is the MicroBlaze a good choice or i... |
hgping | 4/1 | 2008/8/28 07:09 |
| dongle for Xact 5.0 I realize this is a very old program, however I have some designs that I want to use and nothing supports these anymore. I was wondering if anyone has an old dongle for Xact 5.0 they want to sell... |
saigu | 4/2 | 2008/8/28 06:26 |
| combinatorial logic coding style question Hello all, I am new to here. I've read some threads that very helpful to me and I'm confused about a question. As for combinatorial logic coding, the following coding style is suggested inste... |
scuzt | 4/2 | 2008/8/28 06:10 |
| How the synthesizer working Hai, i am new in this forum and i wonder how the HDL compiler generating the RTL from the HDL code. Thanks and Regards Subin |
zunwang | 22/3 | 2008/8/28 06:26 |
| regarding system verilog IN verfication using system verilog is ther any problem by using $dump and $dumpvars as in verilog. or is it need to use only $vcdpluson |
edu | 3/1 | 2008/8/28 06:22 |
| @ltera EP610 programming I want to build a programmer for the @ltera EP610 epld classic family. Any Help please?? In the datasheet it says that the epld has a security bit "that controls access to the data programmed into ... |
z4120356 | 4/2 | 2008/8/28 06:57 |
| free hdl hi all, if somebody have a soft in order to open a file.VHD regards |
lassa | 20/7 | 2008/8/28 06:51 |
| fpga design flow question hi, what i know is that synthesis is the process of transforming behavioral description of hardware into a netlist of logic primitives and mapping is the process of mapping the logic to the target r... |
naoge | 4/6 | 2008/8/28 06:47 |
| issue of multiplier when fpga to asic conversion... anybody know how the multiplier will be converted when converted from fpga to asic? ie. will there be enough multipliers in asic or not? |
nnxd | 5/4 | 2008/8/28 06:34 |
| Increasing FPGA clock frequency I've been reading through quicklogic's application notes and I found this: |
scuzt | 6/1 | 2008/8/28 06:39 |
| ADC and Memory design Hello guys, For my school project we are building a PC digital oscilloscope with a bandwidth of 10mhz and I need help with the design. I want to sample a signal injected into a ADC and sto... |
knoxville | 4/10 | 2008/8/28 06:34 |
| How to modify my FSM I just try to study FSM. I just wrote a FSM by using verilog. My plan is selling ticket with 15. user are allowed to add 5 or 10. whenever it reach to 15 ticket will come out and back to start st... |
z315 | 3/3 | 2008/8/28 06:49 |
| differences between fpga's and cplds whats the major differences between fpga's and cpld's |
wy830115 | 3/5 | 2008/8/28 06:52 |
| Arithmetic encoder verilog implementation help Hi,All. I implemented huffman encoder for my project, but i used example source code from another implementation of huffman algorithm. I found three implementations of huffman algorithm. I trye... |
chdd | 4/1 | 2008/8/28 06:30 |
| Combinatorial blocking vs non-blocking Just out of curiousity.. if you say make a state machine will a full sensitivity.. does it really matter if you make your assignments either blocking or non-blocking? and if it doesn't.. wha... |
bubulu | 9/8 | 2008/8/28 07:01 |
| USB to JTAG cable Hello guys, I have a Spartan 3 Starter Kit which comes with parallel to JTAG programming cable; however i don't have a parallel port on my laptop. First, I thought a USB to JTAG cable would do my... |
knoxville | 4/3 | 2008/8/28 06:26 |
| Cyclone FPGA embedded configuration... Asking some oppinions here what is the most convenient way to implement FPGA configuration on an embedded platform... - Do you use EPCS devices at all? - Only configure FPGA through CPU and sof... |
knoxville | 3/5 | 2008/8/28 07:04 |
| GAL - programming i want to implement some logic functions in only one chip. how can i programm GAL 16V8-25QJ? is it possible to write the code in vhdl? which tools are needed for this? |
hualeyan | 4/15 | 2008/8/28 06:39 |
| SOFTWARE DEFINED RADIO FOR MOBILE COMM. HI ALL, I am a new member in that forum & I'll be very happy if u helped me get all information I need about mobile communicaton as i am interested in that field Briefly ,I want to ask you about t... |
knoxville | 3/3 | 2008/8/28 06:29 |
| ISE and Matlab ? Do any body know if the ISE can communicate some way with matlab .. i know that there is a tool can do it but iam not sure which one |
dongyea | 7/8 | 2008/8/28 07:06 |
| Spartan3 Does anybody know how much slices does the Microblaze take from the Spratn3 FPGA ? What percentage of FPGA is it ? Thanks in advance |
pdang | 3/4 | 2008/8/28 06:32 |
| I need sample VHDL codes Dear all, I need some VHDL sample codes for the common communication systems modulators and demodulators .. such as QPSK, OQPSK, BFSK, ... and so on.. Can someone tell me where from? Or uplo... |
spacebac | 3/5 | 2008/8/28 06:30 |
| spartan 3e starter kit problem! HELP! hi all; i have a spartan 3e starter kit. i write code with xilinx ise. xilinx ise is generate bit file and i load this file with xilinx impact to fpga. it's ok. i generate prom file from bit file... |
pdang | 4/9 | 2008/8/28 06:21 |
| list of fpga projects? here is the list of project i collect from edaboard.com Final Year Projects invloving FPGA: 1.USB 2.0 Core 2.8051 or 8085 Microprocessor Architecture 3.GMSK,QAM,PSK,etc Modulation using SD... |
ken7976 | 33/19 | 2008/8/28 06:43 |
| Question about ADC and DAC Say that can implemetion ADC or DAV with FPGA or CPLD by VHDL. It is right or wrong ? If it is right, anyone give me some link, documents or source code about this problem. I am using FPGA and CPLD ch... |
yutcxa | 6/13 | 2008/8/28 07:03 |
| SATA testing board I want to do some projects with the SATA protocol. Can anybody provide with me some testing board information? I want the SATA phy chip on the board and I can use the FPGA chip to cope wit... |
ybyygu | 3/6 | 2008/8/28 06:29 |
| I have problem. please help me. Hi, I have a XC9572 trainer kit with parallel JTAG programming,I am able to successfully program the device XC9572 PC84 AEM0037-15C. Now i have purchased the new devices as XC9572 PC84 AMM0701 15C ... |
fusarium | 3/2 | 2008/8/28 06:26 |
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