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| Title | Author | Views/Replies | Posted at |
 regarding test benchguyz do u have any idea how can we write a test bench to test the 8*8 multiplier with all the possible cases without writing them manually... thanks, |
hualeyan | 2/3 | 2008/8/28 04:51 |
| gate level simulation- sdf file how to read clk hii was trying to do gate level simulation using qu(at)rtus and modelsim.the dut is a counter and it works at 411 MHz.now if i write the test bench am i supposed to generate the clock in testbench not... |
ybyygu | 0/2 | 2010/8/1 07:56 |
| Error while simulating transient analysis Hi friends, I have recently copied Cadence from server in our college to my local machine. Everything works fine like starting ICFB, schematic editor and even ADE but when I run simulation, spectre st... |
yutcxa | 0/2 | 2010/8/1 13:29 |
| In DC set_ip_delay or set_op_delay who hi all,while going through a tutorial on DC i got one doubt.create_clock constraints clock to a frequency that design has to work.but if we put set_input_delay who decides these factors.since set_inpu... |
chdd | 0/1 | 2010/7/31 23:18 |
| Warning regarding one net is connecting multiple ports i m getting Warning in synopsys design vision for net connected to multiple ports .....likeWarning: In the design matric_n_14, net 'a_1_' is connecting multiple ports. (UCN-1)Warning: In the design ma... |
saigu | 0/1 | 2010/8/1 09:11 |
| ncelab -coverage Hi folks,Can anyone help me for generating coverage data with cadence NCsim.?Actaully I am facing problem in specifing arguments (constraints) especailly for locating the design unit.I have used >ncel... |
chdd | 0/8 | 2010/8/1 11:13 |
| Start up companies in ASIC design Hi everyone,I am, a new graduate, looking for a ASIC, VLSI or FPGA design work. I will be so glad if you give your suggestions.Thanks |
ybyygu | 0/4 | 2010/7/31 14:31 |
| WLAN OFDM paper very good intro....... |
htc2498 | 3/1 | 2008/8/28 06:10 |
| Critical Path What is meant by Critical Path in a circuit? What is its significance? |
ai8957382 | 0/3 | 2010/7/31 15:12 |
| UPF examples hi,Unified power format is a standart which describe the power intent of a design.I found the user guide of the standart and i understood the commands, but i found a lot of difficulties in writing a p... |
naoge | 0/1 | 2010/8/1 09:43 |
| 4kb 4-ways set associative Cache Design Hi,Are arrays in verilog synthesizable? If yes, then how? Currently I made a long one dimensional vector of regs with a total length of 32768. And the addressing is a bit complex. Also, the RTL Compil... |
z4120356 | 0/1 | 2010/8/1 01:56 |
| posedge Hi all,Below is the verilog code for posedge and negedge flipflops using mux.I have also attached the pictorial representation of the circuit.Verilog code :module mux_ff( clk,in,out_pos... |
mxg330 | 0/1 | 2010/7/31 18:42 |
| wire spreading what do you mean by wire spreading ?How it helps to reduce the coupling capacitance? |
naoge | 0/2 | 2010/7/31 20:25 |
| Remove sub-modules from synthesis result (Design Compiler) Hi! At the moment my standard synthesis script for Design Compiler is something like: |
gao51755775 | 0/0 | 2010/8/1 10:22 |
| soc encounter-how to view all modules hi friendsiam working on cadence soc encounter 8.1After the synthesis iam importing my netlist along with sdc and .io file and lef file.Iam able to see the core along with io padson the right side of ... |
wyslnhhh56 | 0/5 | 2010/7/31 14:21 |
| Stupid question about FIFO Hi all,I feel stupid when asking this question but I have to know that.I know that FIFO has pointers and the shift register dont. Can we say that Parallel in parallel out shift register is a FIFO ? |
knoxville | 0/3 | 2010/7/31 22:12 |
| .cdb generation for Encounter Clock Tree Spice Out Hi, I am doing some work with clock trees and have used Encounter to generate the tree. In order to extract a SPICE model of the clock network, Encounter requires a .cdb file. I managed to find one ... |
rickli | 0/2 | 2010/7/31 14:32 |
| interview question.combinational circuit frequency division 1)Design a simple circuit based on combinational logic to double the output frequency2)Design a COMBINATIONAL circuit that can divide the clock frequency by 2.thanks |
btcdtc | 0/1 | 2010/7/31 13:12 |
| urgent help on ncsim error required.. ncsim: *F,VIFCRF (/project/../../): Virtual interface reference was compiled for width=1 but has actual width=6 in interface instance ips_if.what to do...i am usiing ncsim |
dongyea | 0/1 | 2010/7/31 22:59 |
| Circuit for Clock Divide by 5 and 50 % duty cycle (urgent) Hi All,Please help me it's urgent................. |
yutcxa | 0/3 | 2010/7/31 13:23 |
| Gray counter simulation using ModelSim 6.2 c Here is a code for Gray counter which I downloaded form synopsys websitemodule DW_cntr_gray_inst (inst_clk, inst_rst_n, inst_init_n, inst_load_n,inst_data, inst_cen, count_inst);parameter inst_width =... |
addxjyx | 0/4 | 2010/8/1 01:41 |
| digital interview questions with answers? can anyone tell me some websites which gives digital interview qns with solutions?actually im getting many questions but not getting proper solutions..so can anyone help me? |
booksir | 0/1 | 2010/7/31 10:30 |
| finger gates what are finger gates and bend gates shiv |
stgod | 2/2 | 2008/8/28 05:19 |
| filler cells Filler cells can be inserted before or after routing. But why it is better to insert filler cells after routing?thanx |
yutcxa | 0/1 | 2010/7/31 12:19 |
| STA and Logic Simulation Can you sugest possible reasons for the following conditions?1) STA passes but simulation fails on the same logic path.2) Simulation passes but STA fails on the same logic path.thanx |
fujun2013 | 0/1 | 2010/7/31 17:22 |
| Timing nightmare after clock tree synthesis Imagine this scenario.The timing requirement of a design is met after the physical synthesis step.Clock tree synthesis is then performed and all the clock trees meet the skew and latency specification... |
hgping | 0/1 | 2010/7/31 04:25 |
| can you explain to me the behavior of isolation cell? can you explain to me the behavior of this cell? |
fujun2013 | 0/1 | 2010/7/31 13:14 |
| time complexity and layout Hi allI have two same delay circuit ,but "time complexity" are not same.Could you tell me the "time complexity" in a circuit whether influence the quality of CHIP layout ? why?thanks |
398338 | 0/1 | 2010/7/31 11:28 |
| Questions about general ASIC design. Hi.I have a few questions about ASIC design. I tried some searches on the forum and found little general information. It was mostly specific on one thing.My knowledge:I am quite new to ASIC design and... |
398338 | 0/0 | 2010/8/1 01:07 |
| 8-bit adder Hi All,We have a project to implement an 8-bit carry lookahead adder in cmosp18 technology. Do you have any suggestions on what type of logic to use? At the moment, we are thinking of implementing a l... |
z4120356 | 0/2 | 2010/7/31 12:53 |
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