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| Title | Author | Views/Replies | Posted at |
 IEEE1149.1 JTAG spec needPlease send me the IEEE1149.1 JTAG specifications |
ybyygu | 1/2 | 2010/9/6 10:37 |
| Doubt STA related to Input to Reg path, explanation request Hi all,I have read in some PPT that for maximum freq of clock we check for following timing paths for maximum delay : 1. Reg to Reg2. Reg to output 3. Input to output My question is that why we donot ... |
netlgc | 1/3 | 2010/9/6 21:17 |
| SVA Are Assertions Synthesisable... ??? If not the how come Formal Verification possible...??? |
nnxd | 1/10 | 2010/9/6 09:39 |
| Design combinational circuit interview question Design a combinational circuit which gives high output when any 2 bits of 8 bit register are high. Can that be extended such that 3 bits 4 bits...etc |
zunwang | 1/1 | 2010/9/6 16:33 |
| Is anyone using the CoWare LISATek Product Family? If you're using CoWare's LISATek tools I'd like to hear what you think of them. |
scuzt | 1/3 | 2010/9/6 20:29 |
| DFF Hold/setup and jitter Hello edaborders,I have two questions about jitter and dffs working condition.1- If a dff has a hold time of 60 ns setup time of 70ns. Can it work with a clock signal with a 30 ps peak to peak jitter ... |
ai8957382 | 1/2 | 2010/9/6 03:40 |
| Routing using Cadence Encounter I want to extract the routing for specific nets after doing the routing using Cadence Encounter. Which files have that information ?Thanks in advance. |
wy830115 | 1/3 | 2010/9/6 10:05 |
| About Calibre, How to Add label automaticaly For physical design, I first use Synopsys Astro, and than dump the gds file to Calibre for LVS. The problem is that if there are many ports in the design, I have to add the labels one by one manually.... |
lassa | 1/5 | 2010/9/6 04:34 |
| need help (SoC Encounter generateLef error) Hi all, I am using cadence soc encounter 4.1 and I have the following problem:I got a clf file generated by TSMC memory compiler,while using the (generateLef) command in soc encounter to generate a .l... |
fujun2013 | 1/2 | 2010/9/6 15:07 |
| update sdio site h**p://bknpk.no-ip.biz/SDIO/sdio_1.html |
ai8957382 | 1/1 | 2010/9/6 09:51 |
| How to Control clock gating in DFT Hello all, In my design i have manuallly instantiated latch based clock gating. When i do dft_drc it reports error. Warnings: clock pin CK of DFF is not active when clocks are set on. i did chang... |
naoge | 1/4 | 2010/9/6 16:46 |
| how to verify the unique_id? hi , now i'm going to verify the unique_id after postlayout. What shall i do. and is the unique_id is ok after reset?thanks first |
z315 | 1/1 | 2010/9/6 09:13 |
| design compiler contraints 2 clocks Dear all I am working on making a .sdc file from synthesis. in my design theare are 2 clocks. now my question is how to define the relation between the clocks in .sdc file for the following condition ... |
fusarium | 0/0 | 2010/9/6 23:01 |
| A question about the clock define in Tetramax Hi, i use Tetramax to generate test patterns first time. I want to know how to define a test clock when we got post-layout netlist. Who can tell me? Thanks in advacne. |
mxg330 | 1/1 | 2010/9/6 14:49 |
| TDK Can anybody elaborate what is TDK and PDK?. How it differs from each other?. |
ken7976 | 1/2 | 2010/9/6 08:52 |
| pseudo-random permutation hi,im working on the image watermarking proj. i want to know what is meant by 'permute a image to disperse its spatial relationship'. could you please me..andthe use of linear feedbackshift register ... |
yutcxa | 0/0 | 2010/9/6 21:31 |
| DFT Question about hard IP scan Hi,I have a module A:module A()B B()endmoduleThe B is a hardware IP, and it is Performed Scan Replacement.Now I want to insert scan in my design A,and route the flip-flop in IP B which is already scan... |
pdang | 1/8 | 2010/9/6 12:16 |
| how to make following code with high impedance synthesizable hi freinds , i am having problem regarding high -Z in my design .My design is not able to be synthesized in design compiler . In my design i need to block some ports for some condition .my raw code is... |
398338 | 0/0 | 2010/9/6 20:53 |
| MANUFACTURINGGRID in lef file Can you specify how I add manufacturing grid in a lef file used by Encounter (Cadence).The syntax:MANUFACTURINGGRID 0.005; doesn't work. The tech.lef file is not accepted.Thank you in advance. |
knoxville | 1/1 | 2010/9/6 07:21 |
| High-speed clock recovery unit based on a phase aligner -REQ Dear All,can any one provide me the following paper."High-speed clock recovery unit based on a phase aligner".Or any informative material on "CLOCK RECOVERY UNIT"Thanks in advance. |
pdang | 1/2 | 2010/9/6 07:30 |
| epson cartridge chip reset? a month ago a buy a printer made by epson model C42.it came with a good price and ofcourse with an easter egg.the cartrige is hardware protected by a csic chip(i think).so you can`t refill it because ... |
spacebac | 5/10 | 2008/8/28 06:10 |
| How to do RAM Failure Analyis? Hi,A problem about RAM Failure analysis.Some chips is failed after shipping to customers. After functional-level diagnoising, we found a very big size RAM block is failed, several bit-cell is stuck-at... |
lassa | 1/2 | 2010/9/5 22:34 |
| Effect of Process Variations on Clock Skew How I mathematically model the effect of Process Variations on Clock Skew?Process Variaitons in the sense: Gate Length, Width, Channel Length doping etc..Could you please suggest me any books where fr... |
booksir | 1/2 | 2010/9/6 05:42 |
| Help me in SOC encounter............ Hello Sir,After typing "encounter |
398338 | 0/0 | 2010/9/6 18:27 |
| How I can check if there is external cells referenced in gds How I can check if there is external cells referenced in gds file. PLease give me a resume of gds syntaxe. |
398338 | 3/2 | 2008/8/28 05:16 |
| Actel's SYSMGMT-DEV-KIT Hi All,Right now I am working on (Actel |
htc2498 | 0/0 | 2010/9/6 18:10 |
| How to locate out fault location in design Hi,How can we find out fault location in a chip using scan chain design.I want to know how can we identify the fault location if the fault exists in the design.Are there any methods or algorithms to f... |
naoge | 1/4 | 2010/9/5 19:21 |
| pin tapping hi all.... during floorplan...inspite of declaring all the pin access points of pad cells.... there is power open during pad pin tapping ...... what could be the reason regards aswin |
lassa | 3/2 | 2008/8/28 05:04 |
| Behavioral Model for Multiplier Control with Adder How can i make a 4x4 multiplier using only half adder,full adder,8 bit shift register? |
htc2498 | 1/1 | 2010/9/5 23:43 |
| Does anyone know how to verify CDR circuit? For it involves analog PLL,so makes it hard to verify.I want to know: have any tools to verify the mix-signal system? Now i have Specman E and Hsim,can i just put the hspice netlist into verilog netl... |
spacebac | 1/3 | 2010/9/6 04:01 |
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