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| Title | Author | Views/Replies | Posted at |
 cpp testcase and verilog codeHi suppose v write testcase in cpp. How does it apply vectors to verilog module ? |
knoxville | 1/3 | 2008/8/28 05:02 |
| How to add new device to precision synthesis... I am using Old version of Precision Synthesis... It has some devices listed(Eg : @ltera)....but i am going to use a new device(Stratix @ltera) and how to add that device and its properties to my Ol... |
z4120356 | 1/1 | 2008/8/28 05:02 |
| Query in generating input values hi all how to force/generate an input of 256 values at a stretch in MODEL-SIM |
ct731 | 1/0 | 2008/8/28 05:02 |
| Solar cell simulation tool.... Hi. It tried to search the tool which is various, but there was not a possibility of searching the simulation tool which relates with a solar cell. When maybe with solar battery plan the m... |
z315 | 1/0 | 2008/8/28 05:02 |
| what is the core limted design and pad limited design? what is the core limted design and pad limited design? |
spacebac | 1/3 | 2008/8/28 05:02 |
| why we need clock transtion(edge triggering) for flip-flop hello guys , why we need clock edge transtion ( either fall or rise ) for design of flip-flop |
bubulu | 13/8 | 2008/8/28 05:02 |
| about USB Bulk Bandwith ? Let's see a table from USB2.0 spec, table5-10. Data Max bandwith Microframe Max Bytes Bytes/ Payload (byte/second) Bandwith Transfers Remaining Micro... |
spacebac | 1/1 | 2008/8/28 05:02 |
| 65 nm Signals Specification Hi members, Please who can tell me what is the rise/fall Time to gate a 65 nm CMOS transistor. How to determine it. Thanks in advance for your replies. |
yvling | 2/12 | 2008/8/28 05:02 |
| Design Verification with e Hi can anybody send me the soft copy for " Design Verification with e " by samir Palnitkar Regards rajesh |
lassa | 2/3 | 2008/8/28 05:02 |
| field oxide, gate oxide, thin oxide What is the difference between field oxide, gate oxide and thin oxide ?? Can anyone explain me clearly i am having some confusion in this plz explain me in detail Bye take care |
htc2498 | 1/2 | 2008/8/28 05:02 |
| What does 232 in RS-232 refers to.........? What does 232 in RS-232 refers to.........? Thanks |
lassa | 2/2 | 2008/8/28 05:02 |
| Astro Vs SOC encounter hi, Can enybudy suggest me which one is better tool for perticular power critical design power ? and why ? astro ---> synopsys or soc encounter ----> cadence |
nnxd | 1/3 | 2008/8/28 05:02 |
| VHDL-AMS i am kind of new in VHDL-AMS and i am trying to make a simple behavior model of a sample and hold stage using VHDL-AMS, it should act on the positive edge of the pin "clk" then capture the voltage of ... |
btcdtc | 1/3 | 2008/8/28 05:02 |
| Free Seminar on SystemVerilog, Bangalore Jan 5th Free Seminar on SystemVerilog |
anuo2008 | 2/0 | 2008/8/28 05:02 |
| Basics of level shifters hi am trying to understand how the level shifters work ,thier construction and operation, i know some basic points like these are needed in multivoltage domain wheere signals are crossing the ... |
ybyygu | 3/3 | 2008/8/28 05:02 |
| DDR SDRAM Hi ! I have a question on DDR-SDRAM. Why is it that we dont have a transition from READ to WRITE or READ to WRITE with AUTOPRECHARGE ? Thanks! Ravi |
nnxd | 1/3 | 2008/8/28 05:02 |
| VHDL-AMS question hello, is it possible to use the VHDL tool to write in it VHDL-AMS code like FPGA tool? or i must add some libraries to make this allowed? thanks in advance |
knoxville | 4/1 | 2008/8/28 05:02 |
| Depth of Async FIFO How to calculate Depth of Async FIFO in all possible scenarios. |
wyslnhhh56 | 3/2 | 2008/8/28 05:02 |
| macro model timing in encounter dear all i wanted to know on wat bases we can decide upon the macro model timing in encounter for clock specification. for example I have some memory elements in design which I want to include the... |
hualeyan | 3/1 | 2008/8/28 05:02 |
| frontend flow Hi, Can anyone explain about the front end flow (semi custom flow) i.e right from specs to gate level netlist. I shall be delighted if anyone can direct me to any links if possible. thx Ni... |
rickli | 2/9 | 2008/8/28 05:02 |
| Anyone Can Share Synopsys IC compiler Online PDF files ? Anyone Can Share Synopsys IC compiler Online PDF files ? 2006.06 Br |
ken7976 | 1/4 | 2008/8/28 05:02 |
| density of the chip If i have done a project in backend vlsi so if my density is more than 100% then wt shd i do? is there anyway to reduce the density to less than 100% I mean to say after post route optimization ... |
gao51755775 | 2/1 | 2008/8/28 05:02 |
| STAMP model for DDR SDRAM? Can anyone help me getting a stamp model for DDR SDRAM? |
wyslnhhh56 | 1/1 | 2008/8/28 05:02 |
| SDF file translate to constraint file under Astro Does anyone have the experience to translate .sdf file to constraint file under Astro? I used the GUI mode as below : >> Netlist In / SDF To Cinstraint There was always showed : ***** SDF... |
fusarium | 1/1 | 2008/8/28 05:02 |
| hook-up option in dftadvisor The primary inputs have the I/O pads connected to them. I would like to use the I/O pads for scan insertion than using the primary inputs directly. Is there an hook up option in dftadvisor that allows... |
fusarium | 1/1 | 2008/8/28 05:02 |
| Where can I get ultra-ata specification Hi folks, Is there anyone who can tell me where can I get ultra-ata specification? Many thanks. |
ybyygu | 2/1 | 2008/8/28 05:02 |
| Help me. suggest me pls hi i m doing m-tech project. i have to design std cell library using Multi Vt CMOS method for low power desin. i need a design to implement using these designed cells. actually choice of cells to be d... |
ken7976 | 3/0 | 2008/8/28 05:02 |
| More -ve slack in in-reg path Hi, I am having more -ve slack in i/p-reg path. Is there is any command to optimize only i/p-reg path in magma. Is there any other way to get ve slack. Prithivi. |
pdang | 1/8 | 2008/8/28 05:02 |
| power on sequence Does anyone konw something about the power on sequcnce in digital circuit and what is the influence of bad power on sequence, thanks? |
zunwang | 1/1 | 2008/8/28 05:02 |
| issues about test patterns generation for ATE my recent responsibility is to generate test patterns for ATE. The DUT is a mixed-signal chip. But i am a new in this domain. would all of you pls give me some suggestions on procedures and common too... |
saigu | 17/2 | 2008/8/28 05:02 |
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